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Alliance Semiconductor, Corp.
Vishay Intertechnology, Inc.
ALSC[Alliance Semiconductor Corporation]
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| Part No. |
aSM5I9350G-32-LT aSM5I9350 aSM5I9350-32-ET aSM5I9350-32-LT aSM5I9350G-32-ET
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| OCR Text |
...-locked loop (PLL) bypass mode `spreadtrak' Output enable/disable Pin-compatible with MPC9350 and CY29350. Industrial temperature range: -40...a divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(a:D) settings, see... |
| Description |
Mechanism, 2-inch, front feed, w/ manual knob, platen detect & cutter (full cut) 200 MHz, OTHER CLOCK GENERaTOR, PQFP32
3.3V 1:10 LVCMOS PLL Clock Generator 200 MHz, OTHER CLOCK GENERaTOR, PQFP32
Mechanism, 2-inch, front feed, w/ manual knob, platen detect & cutter (full cut)
Mechanism, high speed, ELM w/latch lever
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| File Size |
470.31K /
12 Page |
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it Online |
Download Datasheet
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Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
http://
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| Part No. |
aSM5I9351G-32-LT aSM5I9351 aSM5I9351-32-ET aSM5I9351-32-LT aSM5I9351G-32-ET
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| OCR Text |
...-locked loop (PLL) bypass mode `spreadtrak' Output enable/disable Pin-compatible with MPC9351 and CY29351. Industrial temperature range: -40...a divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(a:D) settings, see... |
| Description |
2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer 9351 SERIES, PLL BaSED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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| File Size |
519.79K /
13 Page |
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it Online |
Download Datasheet |
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Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
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| Part No. |
aSM5I9772aG-52-ET aSM5I9772a aSM5I9772a-52-ER aSM5I9772a-52-ET aSM5I9772aG-52-ER
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| OCR Text |
...-locked loop (PLL) bypass mode `spreadtrak' Output enable/disable Pin-compatible with CY29772, MPC9772 and MPC972 Industrial temperature ran...a:C) settings, see Functional Table. These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4... |
| Description |
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 200 MHz, OTHER CLOCK GENERaTOR, PQFP52
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| File Size |
579.30K /
15 Page |
View
it Online |
Download Datasheet |
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ALSC[Alliance Semiconductor Corporation]
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| Part No. |
aSM5I9773aG-52-ET aSM5I9773a aSM5I9773a-52-ER aSM5I9773a-52-ET aSM5I9773aG-52-ER
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| OCR Text |
...-locked loop (PLL) bypass mode `spreadtrak' Output enable/disable Pin-compatible with CY29773, MPC9773 and MPC973 Industrial temperature ran...a:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to... |
| Description |
Octal D-Type Flip-Flops With Clear 20-SO -40 to 85
Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
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| File Size |
620.40K /
16 Page |
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it Online |
Download Datasheet |
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Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
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| Part No. |
aSM5I9774aG-52-ET aSM5I9774a aSM5I9774a-52-ER aSM5I9774a-52-ET aSM5I9774aG-52-ER
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| OCR Text |
...ut-output skew PLL bypass mode `spreadtrak' Output enable/disable Pin compatible with MPC9774 and CY29774aI. Industrial temperature range: -...a and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(a:C) settings, ... |
| Description |
Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85 9774 SERIES, PLL BaSED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer 9774 SERIES, PLL BaSED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
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| File Size |
474.03K /
12 Page |
View
it Online |
Download Datasheet |
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